Addressing processor back-end issues with RCUs

Traditional microprocessors have long benefited from the transistor density gains of Moore's law. Diminishing transistor speeds and practical energy limits however have created new challenges in technology, where the exponential performance improvements we have been accustomed to from previous computing generations continue to slowly cease. These factors signify that while transistors continue to scale and other technological means are researched, the design challenges faced by computer architects will only be temporarily masked before similar challenges are yet again encountered. This work addresses several conventional processors back-end issues by introducing the concept of Reconfigurable Computing Units (RCUs). RCUs employ logical and physical compilation to maintain compatibility with current compilers and ISAs, while supporting an underlying reconfigurable processor architecture. RCUs consist of a variety of execution engines and functional units, connected through a configurable single-cycle multi-hop registerSwitch interconnect. Experimental results demonstrate that RCUs can achieve up to a 2× performance improvement in purely sequential applications with 3× less logic utilization than a conventional CPU back-end.