Circuit techniques for high-speed and low-power multi-port SRAMs

This paper presents a new approach based on current-mode to reduce the energy and improve the speed of write and read accesses in multi-port SRAMs. The design of a pipelined 32/spl times/64 register file that utilizes the above technique is described. Simulation results in a 0.6 /spl mu/m CMOS technology show that the register file can operate at a 500 MHz frequency using a 2.3 V supply.