A cost effective static linearity testing scheme for ADCs

Testing overhead is one the biggest constraint in any electronic system. In ADCs, the challenge is to generate a linear ramp or a DAC with linearity better than the ADC. This paper proposes a simple, cost effective scheme which does not require any high precision component or measurement system. It uses a ramp based approach, where there is no linearity requirement and a VCO to digitize the quantization steps. Sample and subtract capacitors are used to generate the step sizes and maintain the VCO operating point nearly unaltered. Difference in the VCO frequency is measured using a frequencies counter to generate the step size. The difference in frequency directly gives the DNL. INL is further calculated from this. VCO and time domain approach reduce the effect of noise.