Implementation of 64-bit Kogge Stone Carry Select Adder with ZFC for efficient area

Carry Select Adder (CSLA) is one of the faster adder used in many data-processing processors to perform fast arithmetic functions. The speed of operation of such an adder is limited by carry propagation from input to output. This paper discusses about the implementation of linear Carry Select Adder with Kogge Stone Adderwith out ZFC. The Kogge Stone parallel approach will give option to generate fast carry for intermediate stages. From the structure of linear CSLA it is clear that there is scope for reducing the area in CSLA by using a first zero finding logic. 64-bit linear CSLA architecture is implemented with out using multiplexer which reduces area with slight increase in delay. Simulation and Synthesis are carried on Modelsim 6.3 and Xilinx ISE 12.2.