A comparative analysis of 6T, 7T, 8T and 9T SRAM cells in 90nm technology

Static Random Access Memory (SRAM) is a memory that is designed to provide high speed and low power applications. As the technology is shrinking down, the power supply is also scaled down which decreases the noise margin of the SRAM cells. The reduced noise margin further makes more leakage power in the SRAM cells. The main objective of this project is to deal with the power dissipation which occurs normally in the conventional Static Random Access Memory (SRAM) cells during the read and write operation. This problem can be solved by applying dual-threshold-voltage for 6T, 7T, 8T and 9T SRAM Cells. Their respective power dissipation and delay of these cells are calculated and compared. This is implemented in 90nm Generic Process Design Kit (GPDK) using Cadence Virtuoso Schematic Composer and the Spectre as the simulator.