Test power aware STUMP BIST

The testing power is the biggest concern in modern VLSI chip testing which affects the reliability of the chip. The testing power is very greater than the functional power because during the test mode almost all the part of the chip is active which elevates the testing power problem. In this paper a low test power BIST architecture is proposed which employs clock gating and scan staggering to reduce the testing power, and scan chain segmentation to reduce the testing time. From the experiments conducted on ISCAS89 benchmark circuits, the proposed BIST architecture reduces the test power by 56% with 1% area overhead.