Design of full adder/subtractor using irreversible IG-A gate

In recent years, reversible computation has received much attention in the field of low power circuit design. In this paper, an irreversible IG-A gate is presented. The gate is further used to design irreversible full adder/subtractor (IAS). Furthermore, IAS block is utilized to construct n-bit adder and subtractor. Proposed IAS design is analyzed and compared against the existing reversible methods. Features such as, hardware cost, logic calculation and gate count are investigated to show the efficiency of the design. Transistor level design and simulation of IG-A circuit are shown using Cadence OrCAD Lite. The one-bit IAS simulation results are verified using Altera Quartus II and ModelSim software. Simulation results show that the circuit offers reduced hardware complexity as compared to the existing reversible full adder design.