Decoded ultra-high definition video display system

With the evolution from high definition (HD) to ultra-high definition (UHD), we face great challenges of increasing data rate and computational complexity. The solutions to real-time video transmission and display attract much research interest. In this paper, a hardware architecture based on field-programmable gate array (FPGA) is proposed for decoded UHD video display system. In the architecture, efficient memory management and parallel processing are applied to reduce operational frequency and achieve better real-time performance. The design has been successfully implemented on Altera FPGA, whereby 4K UHD video can be displayed on one single 4K screen smoothly.