Low chip area, low power dissipation, programmable, current mode, 10-bits, SAR ADC implemented in the CMOS 130nm technology

In this paper we present a novel successive approximation register (SAR) analog-to-digital converter (ADC) designed for the applications that demand many such converters working in parallel in a single chip. For this reason we have put a special emphasis on a very low chip area and low power dissipation. The ADC operates in the current-mode. The digital-to-analog converter (DAC), which is one of the components of the SAR ADCs, is in this case based on a concept of a two-stage split architecture that allows to obtain higher resolutions without a substantial increase of the chip area. As a result, the circuit implemented in the IHP CMOS 130nm technology occupies the area of only 0.01 mm
²
. At data rate of 0.55 MSamples/s and 10-bits of resolution it dissipates an average power of 13.2 μW. The supply voltage equals 1.2 V. The proposed circuit is programmable. The 2-stage DAC is composed of 10 branches. If smaller resolutions are sufficient, we can select the branches which are used to perform the conversion. This allows to control, to some extent, data rate of the ADC and the power dissipation.