An automated power estimation and optimization methodology

Power consumption is currently a very important criteria in digital system designs, however power analysis and optimization, especially at the gate level and lower levels of design abstraction, is tedious and complicated for most entry level designers. It requires several iterations of simulation and synthesis to generate and apply switching activity and it is also difficult to setup the various electronic design automation (EDA) tools. In this paper we discuss an automated power estimation and optimization flow, using two well-known EDA tools, that eliminates the laborious tasks of setting design parameters and configuring the EDA tools and thus significantly reduces the development time from several days to several hours. The proposed automated power estimation and optimization flow helps digital designers to estimate and optimize the power consumption of designs effortlessly, accurately, and effectively at gate level. The proposed power estimation and optimization flow also maximizes the capabilities of using available modern computational power in order to examine the effects of a wide range of design and implementation parameters on the power consumption, speed, and area complexity. A case study, the implementation of power efficient finite field multipliers, is shown.