Loss estimation and validation of the SCALDO implementation

A low frequency supercapacitor circulation technique coupled with a commercial low dropout regulators(LDO), namely the supercapacitor assisted LDO (SCALDO), can achieve significantly high end-to-end efficiency(ETEE) for linear regulators. The ETEE could be closer to the efficiencies of practical switching regulators, but without having the negative aspects of switching regulators such as RFI/EMI issues and the use of bulky inductors. In these supercapacitor assisted linear regulator topologies, the efficiency improvement compared to linear regulators is given by a special figure of merit, efficiency improvement ratio, which can be in the range of 1.33 to 3 depending on the SCALDO configuration. Compared to the six different possible loss elements in a switching regulator, in the SCALDO technique losses are mainly contributed by equivalent series resistance of the supercapacitor, RDS (on) of the switches, parasitics in the PCB traces and losses due to paralleling of the supercapacitor with a small buffer capacitor in addition to the losses of the LDO stage. This paper presents a Laplace transform-based analytical solution to estimate the losses during the four phases of SCALDO technique with an example for a 12V-to-5V SCALDO converter.