Design of Intelligent Power Saving (IPS) architecture for reducing power and area in NoC

The solution of data loss and deadlock in Network on Chip (NoC) is by using Virtual Channels. Most of the virtual channels included router of one input or output port. The power problem is extremely significant in virtual channels as the router includes five input-output ports. In this Paper, a new architecture proposed Intelligent Power Saving (IPS) for reducing power and area in virtual channels of NoC. The Proposed architecture can concert diverse considerations to reduce the power and optimization area in NoC. Compared to designs with IPS, in a given budget, we prove that reduces 37.31%, 45.79% and 19.26% in power and reduces 49.4%, 25.5% and 14.4% on area, respectively.