A low-power frontend system for fetal ECG monitoring applications

This paper presents a three-channel frontend system for fetal monitoring applications which includes three amplification chains, an ADC and all power management circuitry needed to feed the different building blocks from a single 1.4V supply. The specifications of the proposed system (0.38μV
rms
equivalent input noise, 74.5dB dynamic range and 0.5 to 200Hz signal bandwidth) are determined according to the properties of the fetal electrocardiogram (fECG) signal and realistic user scenarios. A low-power noise-reconfigurable preamplifier topology exploiting power optimization in both voltage and current domain is used, to achieve a Power Efficiency Factor (PEF) of 2.2 for the whole amplification chain. The 12bit SAR ADC is optimized for high resolution and power efficiency. The frontend system is designed in a 0.18μm CMOS process. Simulation results show that that each of the three amplification channels provides a total gain of 60dB a bandwidth of 200Hz, with an input equivalent noise of 0.38μV
rms
. The ADC provides 11.7bit ENOB and a FoM of 14fJ/step, while its sample speed can vary from 500Hz to 10kHz. The whole system consumes a power of 7.8μW when configured for the fECG application.