Implementation a HERIC inverter prototype connected to the grid controlled by SOGI-FLL

This paper presents a feasible implementation of a single phase inverter prototype via a Highly Efficient and Reliable Inverter Concept (HERIC) topology, which is connected to the grid through a phase and frequency synchronization system by means of a Second Order Generalized Integrator — Frequency Locked Loop (SOGI-FLL). The chosen topology for the inverter design-unlike a full H-bridge (FB) inverter-incorporates two transistors in the output aimed at preventing reactive power transfer between the output filter and input capacitor when zero-crossing. Furthermore, proposed inverter implementation presents low leakage currents, and increases HERIC system efficiency. Moreover, the SOGI-FLL chosen for connecting the HERIC inverter to the grid provides — even under harmonic distortion — a fast and accurate frequency tracking. The prototype implementation can be divided into two parts: First, the power inverter HERIC is implemented, which holds four transistors MOSFET IRF730 (400V–10A) in a FB topology, as well as two IGBT transistors GP10NC60KD (600V–10A). In addition, in order to protect all the devices and ensure a well transistor conmmuation, four diodes type SF54 (200V–5A) are located between emisor and collector from all transistors. Second, the synchronization system is implemented on an Arduino Due digital platform.