ASIC realization and performance evaluation of scalable microprogrammed FIR filters using Wallace tree and Vedic multipliers

Finite impulse response (FIR) filter is widely used in digital signal processing (DSP) and communication systems. Multiplication is an essential and complex building block used in the realization of FIR filters. In this paper, Wallace tree and Vedic multipliers are used for efficient realization of sequential and parallel scalable microprogrammed FIR filter architectures. The designs are coded in Verilog hardware description language and realized using LFoundry 150nm standard-cell based technology. ASIC realization results are presented and analyzed in order to evaluate the performance of both FIR filters.