A 3.5–9.5 GHz compact digital power amplifier with 39.3% peak PAE in 40nm CMOS technology

A 3.5-9.5 GHz fully integrated digital power amplifier (DPA) with peak PAE of 39.3% in 40nm CMOS technology intended for a polar transmitter is presented. A compact wideband DPA design technique employing stacked stepped-impedance (SSI) transformer is firstly introduced to improve the power efficiency while tracking optimum load impedance in a wide bandwidth. This is the only reported wideband DPA operating above 3 GHz with a record fractional bandwidth (FBW) of 92.3%. The DPA exhibits peak output power of 22.2dBm and peak drain efficiency of 46.2% with 1.2V supply. The core chip size is only 0.22 mm
²
.