Design for reliability with a new modeling methodology for Chip to Package Interaction

Chip to Package Interaction (CPI) is becoming a critical reliability issue due to the adoption of new materials used for Si backend interconnects like extreme low k (ELK) dielectric, Pb free solder and Cu pillar bumping and the advanced packaging technologies such as high performance flip chip BGA and 2.5D/3D packages. CPI failures are primarily inside the Si die with the typical failure modes such as ELK fracture; crack initiation and propagation at the Cu/ELK interface and the bump interconnect fracture, etc.