Automated, self-aligned assembly of 12 fibers per nanophotonic chip with standard microelectronics assembly tooling

Silicon photonics technology aims to leverage microelectronic chip fabrication facilities to bring disruptive advancements in photonic circuits cost and complexity. However, the large scale deployment of silicon photonics is muted by the difficulty of cost-efficient and scalable, single-mode optical inputs and outputs. To disruptively improve on cost and scalability, we believe that the best approach is to enable existing high-throughput microelectronic packaging tools for single-mode photonic packaging. In this paper, we experimentally demonstrate such approach with automated assembly of standard-fiber arrays to photonic chips. We identify the main challenges and solutions to enabling high-throughput pick-and-place tooling for single-mode photonic assembly. These include challenges with fiber handling, placement accuracy and limitations in movement complexity. We present a manufacturability assessment of the employed fiber-to-chip self-alignment. We show through Monte Carlo tolerance analysis an expected manufacturing re-alignment accuracy of <;1.3 um despite initial misalignments of up to ~40 um. We believe the approach proposed and demonstrated here can substantially improve on single-mode optical input and output cost and scalability.

Introduction

Single-mode optical inputs and outputs (I/Os) to photonic chips involve high-accuracy alignment of optical glass fibers to embedded waveguide couplers. Currently, this operation is either manual or partially automated with specialized tooling. This results in low throughput, low scalability and much higher cost than electrical I/Os. In fact, the cost of optical I/Os can exceed the chip cost by an order of magnitude or more and negate gains in chip-level cost and integration complexity attained with planar processing of integrated photonic structures. The negative cost impact of packaging is nowhere larger than in silicon photonics, which is leveraging decades of microelectronic processing to bring the chip itself to a new level of cost efficiency and photonic integration complexity [1], [2]. To enable the large scale deployment of silicon photonics, disruptive improvements in the following areas of optical I/Os are required: •

optical connection cost,

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scalability in optical port count per chip, and

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scalability in manufacturing volume.