Accurate CPM based early design stage SERDES PDN optimization in mobile platform

As the demand of faster data rate and power domain sharing for smaller design area increases, power integrity (PI) gets more vulnerable to self and transfer noises. So it is crucial to analyze the overall PDN requirement for reliable system before fabrication. However, the traditional approach using transistor-level analysis could not be applied for a comprehensive analysis due to limited analysis turn-around time. This paper addresses a novel methodology of power delivery network (PDN) co-optimization from chip to board in early design stage to make sure the PDN quality. Accurate CPM (chip power model) is introduced to overcome the simulation time limitation. Novel design optimization method is proposed to get optimal design parameters under the given constraints. Using the proposed methodology, overall PDN design optimization process has been demonstrated with practical examples. In this case study, package design is enhanced by up to ∼ 30% inductance improvement and the number of board decoupling capacitors ∼ 80% reduction after design optimization.