High speed Manchester Carry chain with carry-skip capability

Design of adder is the most focused area in VLSI systems. In this paper, multi-output domino Manchester carry chain with carry-skip capability is proposed. In the proposed design, even and odd carries are computed independently by two parallel carry chains. Carry-skip capability is applied to the odd carry chain which reduces the worst case critical path delay. The circuits are designed and simulated using Cadence Virtuoso tool with CMOS 180nm TSMC technology and IBM 130nm technology in LT SPICE IV. The proposed 64-bit Double chain Manchester Carry chain with carry-skip Adder shows a delay reduction of 52% compared to the Double chain Manchester Carry chain. The proposed Double chain Manchester carry chain with Carry-skip logic allows the elimination of intermediate buffers, thus retaining its area.