VLSI design and implementation of low-complexity adaptive turbo-code encoder and decoder for wireless mobile communication applications

A low-complexity multi-stage pipeline turbo-code encoder and decoder architecture for wireless mobile communication applications is presented. The VLSI decoder architecture presented in this paper avoids complex operations such as exponent and logarithmic computations. The algorithm simplification results in a very efficient low-complexity suboptimal digital implementation. Furthermore, the communication channel statistical estimation process which involves a large number of complex operations is greatly simplified with minor performance degradation. The architecture incorporates simple decision logic that checks for the iteration termination condition. The number of iterations is made to be adaptive and the power-down mode is incorporated. The entire encoder/decoder is implemented with 0.6-/spl mu/m CMOS technology using the EPOCH computer aided design tool.