A Low-Latency, Energy-Efficient L1 Cache Based on a Self-Timed Pipeline

The design of a low latency, energy-efficient self timed L1 cache is presented. The pipeline integrates Octasic's token-based architecture and a two-phase handshake protocol derived from Click elements. Only standard flip-flops are used as state-holding elements for the pipeline control and data path. Simulations and post-layout static timing analysis were based on a commercial 28nm bulk process. Power analysis indicates a 20% improvement in energy efficiency when compared to the previous synchronous cache for the same throughput and area.