Run time write detection in SRAM

Data reliability of Static Random Access Memory (SRAM) cell is a major issue in deep submicron CMOS technology. In this paper, 8T SRAM cell has been proposed to implement a write failure detection scheme read after write. The cell has also been investigated with the conventional 6T SRAM cell for data stability, performance, write & read power, and area. The proposed cell demonstrates higher data stability specifically during read operation as the cell has high read SNM. The simulations have been carried out on 45nm technology node across the process voltage temperature (PVT) variations.