Design a low latency arbiter for on chip communication architecture

This paper presents a modified dynamic bus arbiter architecture for a system on chip design. A high performance SoC communication architecture based on probability bus distribution algorithm where all masters request are having same priority. However, the arbitration plays a critical role in determining performance of bus distribution based system. When all masters generate the request to access the bus at the same time, arbiter manages the situation using information about previously granted master, priority scheme and existing lottery arbitration scheme. This method solves the problem of granting the same master for more than one consecutive cycle. This method also solves the problem of deciding which master to grant when pseudo random number is greater than total partial sum by employing a priority selection method and information about previous granted master. The modified lottery arbitration scheme based communication architecture removes bus starvation and contention problem. This architecture provides a significant reduction in latencies (up to 78.75%) compared to probability based dynamically configured round robin arbiter scheme. The architecture is modeled in Verilog HDL and some of simulation results are presented.