Reconfigurable decoder for irregular random low density parity check matrix based on FPGA

Method for design of partially parallel reconfigurable LDPC-decoder based on FPGA is presented in the paper. The decoder is able to process messages according to irregular random parity check matrix. The decoder can work with irregular random matrix and makes only small constraints on its structure. Parallel processing with several decoding units is considered. It is shown that decoder based on quad-port memory created on two-port memory can increase throughput in four times.