Electronics and computing in nano-era: The good, the bad and the challenging

Technology scaling, which made electronics accessible and affordable for almost everyone on the globe, has advanced IC and electronics since sixties. Nevertheless, It is well recognized that such scaling has a physical, if not an economical, end and it is getting closer to it. It poses major challenges on manufacturing of high quality and reliable systems: process variations, accelerated degradation aging, as well as external and internal noise are couple examples. On the other hand, today's and future data-intensive and big-data problems (ranging from economics and business activities to public administration, from national security to many scientific research areas) are posing serious challenges on data storage and analysis; the increase of the data size has already surpassed the capabilities of today's computation architectures which suffer from the limited bandwidth (due to communication and memory-access bottlenecks), energy inefficiency, reduced reliability and limited scalability (due to CMOS technology). This talk will first address the CMOS scaling and its impact on different aspects of IC and electronics; the major limitations the scaling is facing (such as leakage, yield, reliability, etc) will be shown. The technology outlook will be analysed in order to extract the challenges w.r.t. design, test and reliability both for near and long terms CMOS technology. IC realization process will be (re)defined while considering the technology trends and business pressure. Possible ways for the realization of future systems will be discussed. Moreover, the need of a new technology will be motivated. Thereafter, an overview of computing systems, developed since the introduction of Stored program computers by John von Neumann in the forties, will be given. Shortcomings of today's architectures to deal with data-intensive applications will be discussed and the need for new architectures will be highlighted. Finally, the talk will introduce a new architecture paradigm for big data problems; it is based on the integration of the storage and computation in the same physical location (using a crossbar topology) and the use of non-volatile resistive-switching technology, based on memristors, instead of CMOS technology. The huge potential of such architecture in realizing order of magnitude improvement will be illustrated by comparing it with the state-of-the art architectures for different data-intensive applications.