Implementing High Data Rate, Low Density Parity Check (LDPC) decoders for large codes using FPGAs

Low Density Parity Check (LDPC) Codes offer remarkable error correction performance and therefore increase the design space for communication systems. When implementation complexity and latency are not system limitations, LDPC codes can offer near Shannon Limit performance by using large code lengths and a high number of iterations in the decoding process. Furthermore, there is a need for increasing data rates for LDPC decoding near the Shannon Limit. This paper considers High Data Rate FPGA implementation issues of LDPC Codes for large LDPC codes. The focus of this paper is on high data rate FPGA architectures based on the Sum-Product Algorithm that support decoding large LDPC codes in FPGAs. The paper begins with an overall discussion of issues surrounding decoding large LDPC codes in FPGAs, followed by a discussion of LDPC code processing complexity. Performance charts and design data are provided to support an implementation approach for high data rate, large LDPC codes and quantify required hardware resources. A discussion of trade space for LDPC code implementation based on FPGA resources is also provided. Finally, an example design is provided to illustrate the concepts discussed in the paper and provide insight into the challenging task of implementing high data rate, LDPC decoders for large codes in FPGAs.