III-V nanowire channel on Si: From high-performance vertical FET to steep-slope devices

MOSFETs using III-V channels with multi-gate architecture and tunnel junctions are promising alternative building blocks for high-performance and low power nanoelectronic circuits. CMOS. In this paper, we review recent advances in direct integration of vertical III-V nanowire (NW)-channel on Si and FET application such as vertical III-V NW surrounding-gate transistors (SGTs) and tunneling FET (TFETs) using III-V NW/Si heterojunctions.