A Compact Test Structure for Characterizing Transistor Variability Beyond $3\sigma $

An addressable array test structure is proposed for characterization of transistor variability beyond 3σ away from the mean. The design of the array is based on very compact basic cells which enable a highly efficient layout which has over three times higher normalized device density than similar arrays. Implementations of a 32k array are demonstrated for placement in a standard wafer scribe lane module. Characterization results based on an advanced high-k/metal gate process show that transistor threshold voltages follow a Gaussian distribution at current levels typically used in digital circuits. Analysis of random and systematic components of variability confirms that there are no systematic spatial gradients across the array and that random variations account for 99% of total variability.