Influence of supply voltage on the multi-cell upset soft error sensitivity of dual- and triple-well 28 nm CMOS SRAMs

Dual- and triple-well bulk CMOS SRAMs fabricated at the 28-nm node were tested using alpha particles and heavy-ions over a range of supply voltages. Dual-well SRAMs have better Multiple Cell Upset (MCU) cross sections and spread for nominal voltage, while triple-well SRAMs are better for reduced voltages. TCAD simulations show that single-event upset reversal due to charge confinement is responsible for improved soft error rate (SER) performance at low voltage operation for triple-well SRAMs.