Ultra-thin line embedded substrate manufacturing for 2.1D/2.5D SiP application

For high density interconnection IC packages of the future, the outlook is for thinner packages with higher routing densities. With that, fine line substrate technology becomes critical. Current organic substrates are limited to line/space larger than 8/8 μm for by conventional semi-additive plating (SAP) technology. It may have yield loss issue due to weak adhesion of line/space less than 5/5 μm, especially in long distance line. But the impact of weak adhesion of fine line is very small in line embedded (LE) substrate because of it is in embedded structure. Line embedded is made by laser patterning of dielectric. Dry film material, chemicals for lithography like developer, and stripper are not needed. The circuits are embedded, and capable of stereo copper features. It can cover FC, CSP, CIS, coreless structures. Line embedded technology can provide better electric performance with lower variation of trench width/depth. It can form fine pitch trench line/space less than 5/5 μm. It also has better design flexibility & reliability than SAP process. In this paper, we will discuss the key of the processes and demonstrate the fabrication of fine line substrate in the coreless process of build-up 5/5 μm line/space by adopting line embedded technology. Line embedded was made by laser direct ablation (LDA) on organic build-up dielectric material. By using core as carrier and build-up dielectric material with finer filler size, the coreless structure has demonstrated lower warpage and good trench capability. Laser ablation process capability also shows excellent trench depth control. In order to get better copper thickness uniformity, novel uniform Cu plating technology on trench, pad, and via has development. Low cost and uniform Cu reduction process was also evaluated and developed. We also evaluated the feasibility of separation after molding. Different types of molding compounds are evaluated and good flatness material is found.