C-based RTL design method for circuit switched network on chips

Network-on-Chips (NoCs) are needed to interconnect the cores which are processors and memories in Systems on Chips (SoCs). For designing new NoCs, highly accurate simulation and efficient design procedure are desired. In this paper, we present C-based RTL design method for circuit switched NoC in which RTL structure of NoC is directly described in dataflow C coding style and a fast simulation and verification model by the same C code. Also, we show how the method is used to accelerate the design and verification of the NoC by designing a simple NoC architecture. The entire C model consists of about 200 lines, including C header file. Also, it generates the RTL descriptions which consists of 1,500 lines of Verilog code.