Experiment to optimize gate leakage by variation in device parameters in SOI DG nMOS

In this paper we try to optimize the Gate leakage current of ultra-thin SOI Double-Gate n-channel MOSFET by varying device parameters such as Si film thickness, Gate length, channel doping, Gate oxide thickness and buried oxide thickness. The ultimate size scaling limits of MOSFET is explored owing to scaling down of critical feature dimension size below 10nm. In this paper, we use a non-equilibrium Green's function (NEGF) approach. The two-dimensional self-consistent Schrodinger-Poisson solver with open boundaries is used to capture the quantum mechanical nature of carrier transport.