HALTs from Hell

HALT testing is described in several books [1,3,4] as a sim ple and quick process to find out how robust a component, circuit board, assembly or system might be. In many books and paper examples, the process is shown as being simple and with meaningful results determined. Real life HALT testing may not always be that easy. Problems may arise even before the HALT starts [1]. Setting up for a HALT may expose issues that add complications. Lessons learned from real world HALT examples may benefit those who perform HALT. Planning for success can become important. HALT execution may need to be modified to obtain meaningful results. Lastly, analysis of anomalies and/or failures may provide better un derstanding of the results. Some days one has to improvise when confronted with problems. This paper will cover some of the difficulties of establishing loads for the Devices Under Test (DUT), problems with monitoring the HALT and being able to understand the DUT response. These examples should represent good lessons learned.