On FHD 300MHz@60fps, intra/inter CU mode decision hardware architecture for the Hypernova H.265 encoder

H.265 (HEVC) is the latest joint video coding standard with ITU-T SG16 WP and ISO/IEC JTC1/SC29/WG11. Its coding efficiency is about two times compared to H.264. However the burden of coding unit (CU) mode decision with rate distortion optimization (RDO) is too costly to implement it with hardware. The key idea of this paper is a novel mode decision architecture to reduce the HW complexity of RDO that is the most effective on an encoder's performance without a noticeable PSNR loss. To shrink the size the Hypernova H.265 encoder uses simplified RDO blocks and shares the transform resources. Its operating clock frequency is 300MHz@60fps on FHD image and BD-BR increase is negligible at 6.02% on hardware aspect. The estimated gate count of its is around 1M.