Design of area and power aware reduced Complexity Wallace Tree multiplier

Multiplier is a vital block in high speed Digital Signal Processing Applications. With the more advance techniques in wireless communication and high-speed ULSI techniques in recent era, the more stress in modern ULSI design under which main constraints are Power, Silicon area and delay. In all the high-speed application to Very Large Scale Integration fields, fast speed and less area is required. There are two approaches to improve the speed of multipliers namely booth algorithm and other is Wallace tree algorithm. Generally, multipliers require high latency during the partial products addition and conventional multipliers have more stages so delay is more. However, in this paper, the work has been done to reduce the area by using energy efficient CMOS Full Adder. To implement the high-speed multiplier, Wallace tree multiplier is designed and it is a three-stage operation, which again leads to lesser number of stages and subsequently less number of transistors .Moreover the gate count is significantly reduced. Multipliers and their associated circuits like half adders, full adders and accumulators consume a significant portion of most high-speed applications. Therefore, it is necessary to increase their performance as well as size efficiency by customization. In order to reduce the hardware complexity which ultimately reduces an area and power, Energy Efficient full adders plays a vital role in Wallace tree multiplier. Reduced Complexity Wallace multiplier (RCWM) will have fewer adders than Standard Wallace multiplier (SWM). The Reduced complexity reduction method greatly reduces the number of half adders with 65-75 % reduction in an area of half adders than standard Wallace multipliers.