Loading [MathJax]/extensions/MathMenu.js
DRAM Refresh Mechanisms, Penalties, and Trade-Offs | IEEE Journals & Magazine | IEEE Xplore

DRAM Refresh Mechanisms, Penalties, and Trade-Offs


Abstract:

Ever-growing application data footprints demand faster main memory with larger capacity. DRAM has been the technology choice for main memory due to its low latency and hi...Show More

Abstract:

Ever-growing application data footprints demand faster main memory with larger capacity. DRAM has been the technology choice for main memory due to its low latency and high density. However, DRAM cells must be refreshed periodically to preserve their content. Refresh operations negatively affect performance and power. Traditionally, the performance and power overhead of refresh have been insignificant. But as the size and speed of DRAM chips continue to increase, refresh becomes a dominating factor of DRAM performance and power dissipation. In this paper, we conduct a comprehensive study of the issues related to refresh operations in modern DRAMs. Specifically, we describe the difference in refresh operations between modern synchronous DRAM and traditional asynchronous DRAM; the refresh modes and timings; and variations in data retention time. Moreover, we quantify refresh penalties versus device speed, size, and total memory capacity. We also categorize refresh mechanisms based on command granularity, and summarize refresh techniques proposed in research papers. Finally, based on our experiments and observations, we propose guidelines for mitigating DRAM refresh penalties.
Published in: IEEE Transactions on Computers ( Volume: 65, Issue: 1, 01 January 2016)
Page(s): 108 - 121
Date of Publication: 27 March 2015

ISSN Information:

Funding Agency:


Contact IEEE to Subscribe

References

References is not available for this document.