A CPLD design of a self-organizing system for data clustering

A hardware design of a self-organizing system is presented in this report. A high performance parallel processor is designed with pipeline modules. The size of this system is programmable within a certain degree. In this paper, we design this system using a target CPLD. In addition, this paper shows the error analysis of floating-point operation to estimate the optimum word length of data for the minimization of circuit resources.