A novel asynchronous control unit and the application to a pipelined multiplier

This paper discusses the technique for asynchronous circuit design using a novel asynchronous control unit. We employ the very commonly used device, pass-transistor multiplexer, to design and implement the asynchronous control unit. Even though the architecture of the control unit is simple, the efficiency is good. A multiplier with pipelined structure has been designed to verify the usefulness of this technique. We use TSMC's 0.6 /spl mu/m SPDM process to design and implement an 8-b/spl times/8-b pipelined multiplier. The HSPICE simulation shows that the feedthrough rate of the inputs can be as high as 250 MHz.