A programmable interpolation filter for digital communications applications

The design, implementation and testing of an interpolation filter IC suitable for digital BPSK and QPSK communications applications is discussed. The multiplierless filter consists of a 41-tap programmable interpolate-by-four pulse-shaping filter and a CIC (cascaded integrator and comb) filter whose interpolation ratio can be any integer between two and 1024. Several techniques such as polyphase decomposition for multirate systems and DC gain compensation schemes are exploited so that both high speed and low power consumption can be achieved with simplified structures. Simulation and test results show this 0.8-/spl mu/m CMOS filter capable of providing 55 dB worst-case image rejection at speeds higher than 140 MHz with a supply voltage of 3 volts. The 41,848-transistor chip was fabricated via the MOSIS service.