A V-band CMOS 90nm PLL

This paper presented a V-band phase-locked loop implemented in 90-nm standard CMOS process. The capacitor bank switching techniques is adopted to increase the VCO tuning range. The VCO's band switching is controlled by the 3-bit digital control circuit. To ensure oscillating at low frequency band, the bias current is adjusted with respect to oscillation frequency. The proposed PLL operates form 39.54 – 43.38 GHz. The measured reference spur is −50.61dBc, and the phase noise is −92 dBc/Hz form 1MHz frequency offset.