New High Performance 1-Bit Full Adder Using Domino Logic

Domino CMOS Circuits are significantly used in high performance very large scale integrated (VLSI) system. Designing a low power with high speed performance VLSI circuit is one of the challenging aspects. Full adder is one of the basic blocks for many circuits for multiplication, division and exponentiation operation. This paper proposed a low power with high speed performance 1-bit full adder using domino approach and also shows a comparative analysis of proposed full adder with other full adder using static approach. The simulations are carried out by TANNER EDA tool using PTM 90nm technology node with 1.1V supply voltage. The results show that the proposed 22T domino full adder consume 54.74% less power as compared to 10T static full adder, 54.35% less power consumed as compared to domino 27T full adder and 3.2% less power consumed as compared to 28T static full adder. The results also depict that the speed of a proposed 22T domino full adder is much faster in comparison to 28T static full adder by 68.163%, 1.70% faster as compared to 27T domino full adder and 99% faster as compared to 10T static full adder.