A 12-bit 400-MS/s SHA-less pipelined ADC

This paper presents a 12-bit 400-MS/s pipelined analog-to-digital converter (ADC) without using a front-end sample-and-hold amplifier. A novel timing diagram is proposed to maximize available settling time of residue voltage and minimize distortion. We adopt time constant matching between the first sub-ADC and the multiplying digital-to-analog converter and dynamic comparators without a pre-amplifier to eliminate aperture error, and employ improved bootstrapped switches to guarantee high sampling accuracy. The prototype ADC is implemented in a 65nm CMOS technology. Simulation results show the proposed timing diagram improves SFDR by 11~17dB and SNDR by about 12dB in the entire Nyquist band. The prototype ADC achieves 83.22-dB SFDR, 71.21-dB SNDR and 11.54 ENOB for a 7.03-MHz 1-V_pp sinusoidal input signal. With a 191.01-MHz input, the SFDR and SNDR maintains above 70dB and 67dB respectively.