Add-select-delay-compare Viterbi decoder for UWB communications in electronic power systems

In ultra-wideband (UWB) communications for power electronic systems, large power consumption and logic resource are occupied by multi-parallel sliding-block Viterbi decoders. A novel add-select-delay-compare architecture for Viterbi decoder is proposed to minimize these consumptions. In this architecture, a nested iteration of add-select and compare-select with balanced settling path is utilized to reduce propagation delay of critical path of add-compare-select and lower down parallel degrees of high throughput rate VD. The 500 Mbps UWB prototype receiver with the proposed add-select-delay-compare VD saves 40.4 % logic resource and 11.2 % power consumption compared with the original receiver.