High-speed and low-power FRAM with a bitline-segmental array

A bitline-segmental array architecture for ferroelectric random access memory (FRAM) is proposed to achieve lower power consumption and higher operation speed, in which the cell array is divided into four local blocks. Compared to the conventional array, the bitline-segmental arrays can decrease the power consumption by about 53 percent and 55 percent for read and write operation respectively. An experimental prototype utilizing the proposed architecture is implemented in 0.35 μ m 3-metal process and functionally verified.