Physically based modeling for stress assessment in MOS devices

For the purpose of boosting the performance of MOS devices, applying mechanical stresses to change the semiconductor's band structure as well as to modulate the conduction mass is an effective and promising approach besides continuing to shrink the critical dimension of the devices. As a result of the stress impact on channel depends upon the layout-induced changes in topography of devices, it is therefore necessary to understand the physical behavior of strained silicon when the stressors such as silicon germanium (SiGe), silicon carbon (SiC) alloys and contact-etch-stop layer (CESL) are introduced. Accordingly, this paper presents a three-dimensional (3D) finite element analysis (FEA) combined with piezo-resistance mobility model to assess device performance in 40nm, 32nm technology node, and beyond. The presented simulation methodology is verified to be excellently reliable as is calibrated directly from electrical data. Based on the confirmed results of mobility gain, several important parameters, such as the recess depth of shallow trench isolation (STI) and channel width, are systematically investigated. It is noted that the stronger vertical stress (Szz) resulting from CESL is the main consequence of the reduction in channel width. Furthermore, the analytical results indicate that the extent of the mechanical effect of bending moment from a tensile CESL would be introduced into a fixed 100 nm narrow channel width of NMOSFETs when the concerned protruding gate width continues to increase.