A 6.25Gb/s CMOS clock and data recovery DLL with anti-harmonic lock

This paper presents a clock and data recovery (CDR) delay locked loop that operates in high frequency while keeping low jitter performance. The data rate can be twice the reference clock frequency. A self-starting-control circuit widens the phase capture range. In order to compensate for the attenuation of channel, an equalizer comprised of two peaking amplifiers is employed in front end of CDR. The circuit is implemented in SMIC 1.2V 65nm CMOS technology. It demonstrates that at 6.25Gb/s data with -20dB attenuation, the periodic jitter of the recovery clock is 14.08ps for a total power consumption of 6.5mW.