An improved CMOS ring oscillator PLL applied in RapidIO communications

A low jitter CMOS ring oscillator phase-locked loop (PLL) is presented in this paper. An improved voltage controlled oscillator (VCO) frequency control method is applied, and additional charge pump switches are used in the designed PLL. The VCO phase noise is −118.65dBc/Hz at 1 MHz offset from 3.125 GHz carrier, and the PLL total output jitter is 1.16ps at 3.125GHz in GlobalFoundries 0.13µm CMOS technology. The PLL locking time is 8µs and the total power dissipation with IO is 9.3mW.