A gate-stress-induced ΔVth model reflecting impact of electric field in IGZO thin film transistors

The modeling study of gate-bias-stress-induced threshold voltage shift (ΔVth) in amorphous indium-gallium-zinc oxide (a-IGZO) thin film transistors (TFTs) is reported. According to the total number of tunneled carriers and the probability in tunneling, saturated ΔVth is obtained, and the impact of electric field in gate insulator on the ΔVth is also incorporated in this model. The result shows that the model is able to predict the ΔVth of IGZO TFT under a positive gate stress. The dependence of the ΔVth on the initial conditions is also analyzed in this paper.