Fault tolerant design validation through laser fault injection [space-based computing systems]

Space based real time applications for high end computing systems require that the system not only be extremely reliable but also tolerant to a hierarchy of adverse events generally referred to as faults. At the Center for Microelectronics Research (CMR) of the University of South Florida (USF), laser soft fault injection for fault tolerant design validation research has been carried out. The technique is based on using a thoroughly controlled laser beam into a Very Large Scale Integrated Circuit (VLSIC) which is a component of an operating computer capable of detecting, logging, and correcting a transient fault and then proceeding with its operation. The test vehicle is a 32-bit processor designed for 100% microcircuit fault coverage in addition to concurrent error detection, reporting, logging, and recovery. Of primary interest is the recovery from transient Single Event Upsets (SEU's) caused by high energy particles. The technique has been demonstrated with two different system level series of tests. The first test routine involved the verification of an initial set up and demo test performed at CMR on an early version of the computer which was designed just to verify that the computer detected and logged a hardware error in the register file of the Central Processing Unit (CPU). A second series of test were designed to observe the incrementing of the error count register and the correlation to the number of laser pulses applied. The complete test setup and test validation strategies including samples of test result are presented.